This invention pertains to a frequency synthesizer circuit for generating an analog signal of digitally step-adjustable frequency wherein a reference oscillator generating a reference signal, a phase comparator, an analog low-pass filter, and a voltage-controlled oscillator (VCO) are cascaded in this order, and wherein the phase comparator is controlled by the VCO.
Such frequency synthesizer circuits in the form of phase-locked loops are widely used and are described in many references; see, for example, R. Best, "Theorie und Anwendungen des Phase-locked-loops", AT-Verlag Stuttgart, 3rd Edition, 1982, pages 85 to 89, especially FIG. 79b. This frequency synthesizer circuit produces a signal which has a fixed, but digitally adjustable frequency ratio to a reference frequency. This is achieved by means of an adjustable frequency divider connected into the feedback path between the VCO output and the phase comparator.
The main disadvantage of the prior art frequency-synthesizer circuits is that the frequency is difficult to adjust in small steps, particularly if the ratio of the VCO's oscillation frequency to the reference frequency lies between about 0.1 and 10. This difficulty is overcome by the use of divide-by-fraction frequency dividers, but at the expense of phase jitter.